Loop filter with noise cancellation

ABSTRACT

A loop filter with noise cancellation includes first and second signal paths, an operational amplifier (op-amp), and a noise cancellation path. The first signal path provides a first transfer function (e.g., a lowpass response) for a first signal. The second signal path provides a second transfer function (e.g., an integration response) for a second signal. The second signal is a scaled version of, and smaller than, the first signal by a factor of alpha, where alpha is greater than one. A capacitor in the second signal path may be scaled smaller by a factor of alpha. The op-amp couples to the first and second signal paths and facilitates summing of signals from the first and second signal paths to generate a control signal having op-amp noise. The noise cancellation path couples to the op-amp and provides a noise cancellation signal used to cancel the op-amp noise in the control signal.

CLAIM OF PRIORITY UNDER 35 U.S.C. §119

The present Application for Patent is a divisional of patent application Ser. No. 11/479,513 entitled “LOOP FILTER WITH NOISE CANCELLATION” filed Jun. 30, 2006 and assigned to the assignee hereof and hereby expressly incorporated by reference herein.

BACKGROUND

I. Field

The present disclosure relates generally to electronics circuits, and more specifically to a loop filter suitable for use in a phase-locked loop.

II. Background

Phase-locked loops (PLLs) are commonly used in many electronics circuits and are particularly important in communication circuits. For example, digital systems use clock signals to trigger synchronous circuits, e.g., flip-flops. Transmitter and receiver systems use local oscillator (LO) signals for frequency upconversion and downconversion, respectively. Wireless devices (e.g., cellular phones) in wireless communication systems typically use clock signals for digital circuitry and LO signals for transmitter and receiver circuitry. Clock and LO signals are often generated with voltage-controlled oscillators (VCOs) operating within PLLs.

A PLL typically includes a VCO, a loop filter, and other circuit blocks. The loop filter receives and filters a phase error signal and generates a control signal for the VCO. The loop filter may be implemented with discrete circuit components that are external to an integrated circuit (IC). To reduce cost and possibly improve reliability, it is desirable to implement the loop filter on the IC. However, the loop filter typically has a large capacitor that would occupy a large area of the IC. Various schemes may be used to reduce the size of the capacitor. Unfortunately, many of these schemes introduce significant amount of noise to the PLL. The noise may degrade performance and may even cause the VCO/PLL to fail specifications.

There is therefore a need in the art for a loop filter suitable for integration on an IC and having good performance.

SUMMARY

An innovative loop filter with noise cancellation is described herein. In an embodiment, the loop filter comprises first and second signal paths, an operational amplifier (op-amp), and a noise cancellation path. The first signal path receives a first signal from a first current source and provides a first transfer function (e.g., a lowpass response) for the first signal. The second signal path receives a second signal from a second current source and provides a second transfer function (e.g., an integration response) for the second signal. The second current source provides alpha times less output current than the first current source, where alpha is greater than one. The second signal is a scaled version of the first signal and is smaller than the first signal by a factor of alpha. The first signal path may comprise a resistor and a first capacitor. The second signal path may comprise a second capacitor that is scaled smaller by a factor of alpha due to the second signal being scaled smaller by alpha. The smaller capacitor size makes the loop filter well suited for integration on an IC.

The op-amp couples to the first and second signal paths and facilitates summing of signals from the first and second signal paths to generate a control signal having op-amp noise. The op-amp and the first and second signal paths may be coupled in various manners, as described below. The noise cancellation path couples directly or indirectly to the op-amp and provides a noise cancellation signal that is used to cancel the op-amp noise in the control signal. The control signal and the noise cancellation signal may be applied to an adjustable circuit element, e.g., a varactor. This circuit element may be controlled by the control signal and may have the op-amp noise cancelled by the noise cancellation signal.

Various aspects and embodiments of the invention are described in further detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and nature of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.

FIG. 1 shows a block diagram of an PLL.

FIG. 2A shows a frequency response of a single-path loop filter.

FIG. 2B shows a frequency response of a dual-path loop filter.

FIG. 3 shows a passive single-path loop filter.

FIG. 4 shows a passive dual-path loop filter.

FIG. 5 shows an active dual-path loop filter with two op-amps.

FIGS. 6A and 6B show active dual-path loop filters with single op-amp.

FIGS. 7A through 7D show active dual-path loop filters with noise cancellation.

FIG. 8 shows loop filter output noise for three loop filter designs.

FIG. 9 shows a dual-path loop filter with noise cancellation and a VCO.

FIG. 10 shows a process for performing loop filtering with noise cancellation.

FIG. 11 shows a block diagram of a wireless device.

DETAILED DESCRIPTION

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

FIG. 1 shows a block diagram of a phase-locked loop (PLL) 100 that includes a phase-frequency detector (PFD) 110, a charge pump (CP) 120, a loop filter (LF) 130, a voltage-controlled oscillator (VCO) 140, and a divider 150. VCO 140 generates an oscillator signal having a frequency that is determined by a control signal V_(CTRL) from loop filter 130. Divider 150 divides the oscillator signal by a factor of N in frequency and provides a feedback signal. In general, N≧1 and may be an integer or non-integer value.

Phase-frequency detector 110 receives a reference signal and the feedback signal, compares the phases of the two signals, and provides a detector signal that indicates the phase difference/error between the two signals. Charge pump 120 generates an error signal I_(CP) that is proportional to the detected phase error. Loop filter 130 filters the error signal and provides the control signal for VCO 140. Loop filter 130 adjusts the control signal such that the phase or frequency of the feedback signal is locked to the phase or frequency of the reference signal.

Loop filter 130 has a frequency response that is typically selected to achieve the desired closed-loop response for PLL 100. For example, the frequency response of loop filter 130 may be selected based on a tradeoff between acquisition and tracking performance and PLL noise performance.

FIG. 2A shows a plot of a frequency response 210 of loop filter 130. Frequency response 210 includes a first pole at direct current (DC), a zero at frequency ω₁, and a second pole at frequency ω₂. The first pole at DC results in a slope of −20 decibels (dB) per decade of frequency from DC to ω₁. The zero at ω₁ results in a flat frequency response from ω₁ to ω₂. The second pole at ω₂ results in a slope of −20 dB per decade from ω₂ onward.

FIG. 3 shows a schematic diagram of a loop filter 310 that can provide frequency response 210 shown in FIG. 2A. Loop filter 310 includes a resistor 324 and capacitors 326 and 328. Resistor 324 and capacitor 326 are coupled in series and between node X and circuit ground. Capacitor 328 is coupled between node X and circuit ground. A current source 322 from charge pump 120 drives node X, which provides the control voltage V_(CTRL) for VCO 140. The desired loop filter frequency response may be obtained by selecting appropriate values for resistor 324, capacitors 326 and 328, and current source 322.

Referring back to FIG. 2A, the location of the zero is determined by resistor 324 and capacitor 326 in FIG. 3, or ω₁=1/R·C₁. The location of the second pole is determined by resistor 324 and mostly capacitor 328, or ω₂≈1/·C₂. Since ω₁ is typically much lower (e.g., an order of magnitude or more lower) than ω₂, capacitor C₁ is typically much larger (e.g., an order of magnitude or more) than capacitor C₂. If loop filter 310 is implemented on an integrated circuit (IC), then capacitor C₁ may occupy a much larger area than capacitor C₂. This may make the integration of loop filter 310 on an IC impractical from the perspective of cost.

To reduce the size of capacitor C₁, loop filter 310 in FIG. 3 may be decomposed into two signal paths. One signal path may provide an integration response, which may be a frequency response with one pole at DC. The other signal path may provide a lowpass response, which may be a frequency response with one pole at frequency ω. Each signal path may be designed with an appropriately sized capacitor. The outputs of the two signal paths may be summed to obtain a control voltage having the desired frequency response for the loop filter.

FIG. 4 shows a schematic diagram of a dual-path loop filter 410 that can provide a frequency response similar to the one shown in FIG. 2A. Loop filter 410 includes a first signal path 420, a second signal path 430, and a summer 440. First signal path 420 includes a resistor 424 and a capacitor 426 that are coupled in parallel and between one input of summer 440 and circuit ground. A current source 422 from charge pump 120 drives resistor 424 and capacitor 426. Second signal path 430 includes a capacitor 434 that is coupled between the other input of summer 440 and circuit ground. A current source 432 from charge pump 120 drives capacitor 434. Summer 440 sums the two inputs and provides the control voltage V_(CTRL) for VCO 140.

First signal path 420 has a transfer function of H₁(s), which may be expressed as:

$\begin{matrix} {{H_{1}(s)} = {\frac{1}{C_{2}} \cdot {\frac{1}{s + {{1/R} \cdot C_{2}}}.}}} & {{Eq}\mspace{14mu} (1)} \end{matrix}$

-   H₁(s) is a lowpass response having one pole at ω₂=1/R·C₂.

Second signal path 430 has a transfer function of H₂(s), which may be expressed as:

$\begin{matrix} {{H_{2}(s)} = {\frac{1}{s \cdot C_{1}}.}} & {{Eq}\mspace{14mu} (2)} \end{matrix}$

-   H₂(s) is an integration response having one pole at DC.

Loop filter 410 has an overall transfer function of H(s), which may be expressed as:

$\begin{matrix} {{H(s)} = {\frac{C_{1} + C_{2}}{C_{1} \cdot C_{2}} \cdot {\frac{s + {{1/R} \cdot \left( {C_{1} + C_{2}} \right)}}{s \cdot \left( {s + {{1/R} \cdot C_{2}}} \right)}.}}} & {{Eq}\mspace{14mu} (3)} \end{matrix}$

FIG. 2B shows a plot of a frequency response 220 of the overall transfer function H(s) for dual-path loop filter 410 in FIG. 4. Frequency response 220 includes a first pole at DC, a zero at frequency ω′₁, and a second pole at frequency ω′₂. Since C₁ is much larger than C₂, the location of the zero is determined by resistor 424 and mostly capacitor 434, or ω′₁≈1/R·C₁. The location of the second pole is determined by resistor 424 and capacitor 426, or ω′₂=1/R·C₂. The desired loop filter frequency response may be obtained by selecting appropriate values for resistor 424, capacitors 426 and 428, and current sources 422 and 432.

The two signal paths 420 and 430 of loop filter 410 provide flexibility in terms of selecting capacitor values. As shown in FIG. 4, current source 422 may provide a current of I_(CP) whereas current source 432 may provide a current of I_(CP)/α, where α>1. This then allows capacitor 434 to be scaled smaller by a factor of α. For example, if α=10 , then capacitor 434 may have a capacitance of C₁/10 and would then be 10 times smaller than capacitor 326 within loop filter 310 in FIG. 3. The smaller capacitor size may allow loop filter 410 to be integrated on an IC.

Dual-path loop filter 410 may be implemented in various manners. Several exemplary designs of loop filter 410 are described below.

FIG. 5 shows a schematic diagram of a loop filter 510, which is one design for loop filter 410 in FIG. 4. Loop filter 510 includes a first signal path 520, a second signal path 530, and a summing circuit 540. First signal path 520 includes a resistor 524, a capacitor 526, and an op-amp 528. Resistor 524 and capacitor 526 are coupled in parallel and between an inverting input and an output of op-amp 528. A current source 522 from charge pump 120 drives the inverting input of op-amp 528. Second signal path 530 includes a capacitor 534 that is coupled between a non-inverting input of an op-amp 546 and circuit ground. A current source 532 from charge pump 120 drives the non-inverting input of op-amp 546 and capacitor 534. Summing circuit 540 includes resistors 542 and 544 and op-amp 546. Resistor 542 is coupled between the output of op-amp 528 and an inverting input of op-amp 546. Resistor 544 is coupled between the inverting input and the output of op-amp 546. Op-amp 546 provides the control voltage V_(CTRL) for VCO 140.

Loop filter 510 achieves the goals of providing the desired loop filter frequency response and reducing the size of capacitor 534. However, loop filter 510 uses two op-amps to achieve the desired function. These op-amps generate op-amp noise that appears in the control voltage V_(CTRL). Furthermore, a large (e.g., rail-to-rail) voltage swing appears at the non-inverting input of op-amp 546.

FIG. 6A shows a schematic diagram of a loop filter 610, which is another design for loop filter 410 in FIG. 4. Loop filter 610 includes a first signal path 620, a second signal path 630, and a summing circuit. First signal path 620 includes a resistor 624 and a capacitor 626. Resistor 624 is coupled between the output of an op-amp 636 and node A. Capacitor 626 is coupled between node A and circuit ground. A current source 622 from charge pump 120 drives node A, which provides the control voltage V_(CTRL). Second signal path 630 includes a capacitor 634 that is coupled between a non-inverting input of op-amp 636 and circuit ground. A current source 632 from charge pump 120 drives capacitor 634. Op-amp 636 performs the summing function.

Loop filter 610 achieves the goals noted above using only one op-amp 636. However, this op-amp generates op-amp noise that appears in the control voltage V_(CTRL). Furthermore, a large voltage swing appears at the non-inverting input of op-amp 636.

FIG. 6B shows a schematic diagram of a loop filter 612, which is yet another design for loop filter 410 in FIG. 4. Loop filter 612 includes first signal path 620, a second signal path 640, and a summing circuit. Second signal path 640 includes a capacitor 644 that is coupled between an inverting input and an output of an op-amp 646. A current source 642 from charge pump 120 is also coupled to the inverting input of op-amp 646 and drives capacitor 644. Current source 642 is coupled in a direction that is opposite of current source 632 in FIG. 6A. This is because current source 642 is coupled to the inverting input of op-amp 646 in FIG. 6B whereas current source 632 is coupled to the non-inverting input of op-amp 636 in FIG. 6A.

Loop filter 612 achieves the goals noted above using only one op-amp and avoids a large voltage swing at the inverting input of op-amp 646. However, op-amp 646 generates op-amp noise that appears in the control voltage V_(CTRL).

In general, noise from an op-amp in a loop filter may significantly degrade phase noise of a VCO that is controlled by the loop filter. The amount of degradation was measured for one exemplary PLL design. For this PLL design, the integrated phase noise of a VCO was first measured with the PLL using an off-chip passive loop filter, e.g., as shown in FIG. 3. The integrated phase noise of the same VCO was found to degrade by approximately 3 dB when the PLL employs an on-chip active dual-path loop filter with an op-amp, e.g., as shown in FIG. 6A or 6B. This amount of degradation in phase noise may cause the VCO to have smaller phase noise margin or, even worse, to fail phase noise specifications.

In an aspect, an innovative dual-path loop filter with noise cancellation is described. Noise cancellation refers to a process that attempts to cancel, reduce, suppress, or mitigate noise. The innovative loop filter described herein achieves the goals of providing the desired loop filter frequency response and reducing capacitor size without introducing a significant amount of op-amp noise. The innovative loop filter is thus suitable for integration on an IC. Furthermore, good phase noise performance may be achieved for a VCO that is controlled by an on-chip loop filter with noise cancellation.

FIG. 7A shows a schematic diagram of an embodiment of a dual-path loop filter 710 with noise cancellation. Loop filter 710 is a novel design for loop filter 410 in FIG. 4 and may be used for loop filter 130 in FIG. 1. Loop filter 710 includes a first signal path 720, a second signal path 730, a summing circuit, and a noise cancellation path 740. First signal path 720 includes a resistor 724 and a capacitor 726 that are coupled as described above for resistor 624 and capacitor 626, respectively, in FIG. 6A. A current source 722 from charge pump 120 drives the first signal path. Second signal path 720 includes a capacitor 734 that is coupled as described above for capacitor 644 in FIG. 6B. A current source 732 from charge pump 120 drives the second signal path. An op-amp 736 performs the summing function for signals from the two signal paths.

In the embodiment shown in FIG. 7A, noise cancellation path 740 includes a resistor 742 and a capacitor 744. Resistor 742 is coupled between the inverting input of op-amp 736 and node B. Capacitor 744 is coupled between node B and circuit ground. Resistor 742 and capacitor 744 have the same −3 dB bandwidth as resistor 724 and capacitor 726. This results in the op-amp noise at node B having similar characteristics as the op-amp noise at node A (at least at low frequencies).

Node A provides the control voltage V_(CTRL) for VCO 140. Node B provides a noise cancellation voltage V_(N). A variable capacitor (varactor) 750 is coupled between nodes A and B. The voltage across varactor 750 may be given as: V_(VAR)=V_(CTRL)−V_(N). Since V_(N) is at virtual ground in the embodiment shown in FIG. 7A, the voltage across varactor 750 is essentially equal to V_(CTRL).

Loop filter 710 operates as follows. For first signal path 720, since op-amp 736 has low output impedance, current source 722, resistor 724, and capacitor 726 are essentially coupled in the same manner as current source 422, resistor 424, and capacitor 426 in FIG. 4. For second signal path 730, since op-amp 736 also has high input impedance, current source 732 and capacitor 734 are essentially coupled in the same manner as current source 432 and capacitor 434 in FIG. 4. The inverting input of op-amp 736 is at virtual ground because the non-inverting input is coupled to circuit ground. Hence, the voltage swing at the inverting input of op-amp 736 is minimal Op-amp 736 provides an output voltage that is determined by the current I_(CP)/α from current source 732 and the capacitance C₁/α of capacitor 734. The op-amp output voltage is converted to current via resistor 724 and summed with the current I_(CP) from current source 722 at node A.

For clarity, all op-amp noise is referred to the output of the op-amp in the following description. The noise from op-amp 736 travels via a first op-amp noise path composed of resistor 724 and capacitor 726. The noise from op-amp 736 also travels via a second op-amp noise path composed of capacitor 734, resistor 742, and capacitor 744. The op-amp noise via the second noise path is approximately equal to the op-amp noise via the first noise path, especially at low frequencies. The same op-amp noise is then presented to both ends/terminals of varactor 750. The op-amp noise at one end of varactor 750 essentially cancels the op-amp noise at the other end of the varactor. Varactor 750 would then observe just the desired signal from current sources 722 and 732, assuming that the noise cancellation is effective.

FIG. 7B shows a schematic diagram of an embodiment of a dual-path loop filter 712 with noise cancellation, which is another novel design for loop filter 410 in FIG. 4. Loop filter 712 includes all of the circuit elements in loop filter 710 in FIG. 7A, except for resistor 742 and capacitor 744. In the embodiment shown in FIG. 7B, for first signal path 720, capacitor 726 is coupled between node A and the output of op-amp 736 (instead of between node A and circuit ground). For noise cancellation path 740, the inverting input of op-amp 736 is coupled via a wire line 746 to node B, which provides the noise cancellation voltage V_(N). The first op-amp noise path is via resistor 724 and capacitor 726. The second op-amp noise path is via capacitor 734 and wire line 746. The op-amp noise via the second noise path is similar to the op-amp noise via the first noise path, especially at low frequencies. Hence, the op-amp noise is essentially canceled at varactor 750, which then observes mostly the desired signal from current sources 722 and 732.

FIG. 7C shows a schematic diagram of an embodiment of a dual-path loop filter 714 with noise cancellation, which is yet another novel design for loop filter 410 in FIG. 4. Loop filter 714 includes all of the circuit elements in loop filter 712 in FIG. 7B. In the embodiment shown in FIG. 7C, for first signal path 720, resistor 724 and capacitor 726 are coupled in parallel and between the inverting input and the output of op-amp 736. Current source 722 is also coupled to the inverting input of op-amp 736 (which is node A) and drives resistor 724 and capacitor 726. For second signal path 730, capacitor 734 is coupled between node B and the output of op-amp 736. Current source 732 is also coupled to node B and drives capacitor 734. For noise cancellation path 740, current source 732 and capacitor 734 are coupled via wire line 746 to node B, which provides the noise cancellation voltage V_(N).

The first op-amp noise path is via resistor 724 and capacitor 726. The second op-amp noise path is via capacitor 734 and wire line 746. The op-amp noise via the second noise path is similar to the op-amp noise via the first noise path, especially at low frequencies. Hence, the op-amp noise is essentially canceled at varactor 750.

FIG. 7D shows a schematic diagram of an embodiment of a dual-path loop filter 716 with noise cancellation, which is yet another novel design for loop filter 410 in FIG. 4. Loop filter 716 includes all of the circuit elements in loop filter 712 in FIG. 7B. In the embodiment shown in FIG. 7D, for first signal path 720, resistor 724 and capacitor 726 are as described above for FIG. 7B. For second signal path 730, capacitor 734 is coupled between node B and the output of op-amp 736. Current source 732 is also coupled to node B and drives capacitor 734. Op-amp 736 has its inverting input coupled to its output and its non-inverting input coupled to circuit ground. Op-amp 736 thus operates as a unity gain buffer. For noise cancellation path 740, current source 732 and capacitor 734 are coupled via wire line 746 to node B, which provides the noise cancellation voltage V_(N).

The first op-amp noise path is via resistor 724 and capacitor 726. The second op-amp noise path is via capacitor 734 and wire line 746. The op-amp noise via the second noise path is similar to the op-amp noise via the first noise path, especially at low frequencies. Hence, the op-amp noise is essentially canceled at varactor 750.

FIGS. 7A through 7D show several embodiments of a dual-path loop filter with noise cancellation. The dual-path loop filter with noise cancellation may also be implemented with various other designs, and this is within the scope of the present invention. In general, the loop filter provides a first output signal having a desired signal plus unwanted op-amp noise and a second output signal having the unwanted op-amp noise. A circuit element (e.g., a varactor) that is applied with the first and second output signals would then observe similar op-amp noise at both terminals, and the op-amp noise would essentially be canceled. The effectiveness of the noise cancellation is dependent on how well the op-amp noise in the second output signal matches the op-amp noise in the first output signal. The first and second op-amp noise paths may be designed so that the op-amp noise in the second output signal matches the op-amp noise in the first output signal over a frequency range of interest.

FIG. 8 shows plots of output noise for several exemplary loop filter designs. Plot 810 shows an output noise response for an off-chip loop filter with passive components, e.g., as shown in FIG. 3. Plot 812 shows an output noise response for an on-chip active dual-path loop filter without noise cancellation, e.g., as shown in FIG. 6A or 6B. Plot 812 indicates that the op-amp noise adds significantly to the loop filter output noise at low frequencies. Plot 814 shows an output noise response for an on-chip active dual-path loop filter with noise cancellation, e.g., as shown in FIG. 7B. Plot 814 indicates that the op-amp noise is essentially canceled with the noise cancellation signal V_(N). The noise performance of the on-chip active dual-path loop filter with noise cancellation is comparable to the noise performance of the off-chip passive loop filter.

FIG. 9 shows a schematic diagram of dual-path loop filter 712 and an embodiment of VCO 140 in FIG. 1. In this embodiment, VCO 140 is implemented with complementary metal-oxide semiconductor (CMOS) and includes an amplifier 910 and a resonator tank circuit 920.

Amplifier 910 is composed of N-channel MOS (N-MOS) transistors 912 a and 912 b and P-channel MOS (P-MOS) transistors 914 a and 914 b. Transistors 912 a and 914 a form a first inverter, and transistors 912 b and 914 b form a second inverter. Transistor 912 a has its source coupled to circuit ground, its drain coupled to the drain of transistor 914 a, and its gate coupled to a node V_(OSC) ⁺. Transistor 914 a has its source coupled to a power supply, V_(DD), its drain coupled to the drain of transistor 912 a, and its gate coupled to node V_(OSC) ⁺. Transistors 912 b and 914 b are coupled in similar manner as transistors 912 a and 914 a, respectively. Nodes V_(OSC) ⁺ and V_(OSC) ⁻ represent the input and output, respectively, of the first inverter. Nodes V_(OSC) ⁻ and V_(OSC) ⁺ also represent the input and output, respectively, of the second inverter. The first and second inverters are thus coupled in series and in a closed-loop configuration. Nodes V_(OSC) ⁺ and V_(OSC) ⁻ represent the differential output of VCO 140 and provide the oscillator signal.

Resonator tank circuit 920 is composed of an inductor 922, varactors 924 a and 924 b, capacitors 926 a and 926 b, and resistors 928 a and 928 b. Inductor 922 is coupled between nodes V_(OSC) ⁺ and V_(OSC) ⁻. Varactor 924 a has its anode coupled to node A and its cathode coupled to node Sa. Capacitor 926 a is coupled between node Sa and node V_(OSC) ⁻. Resistor 928 a is coupled between node B and node Sa. Varactor 924 b, capacitor 926 b, and resistor 928 b are coupled in similar manner as varactor 924 a, capacitor 926 a, and resistor 928 a, respectively.

In tank circuit 920, varactors 924 a and 924 b provide variable capacitance that may be adjusted by the control voltage V_(CTRL) from loop filter 712. The capacitance of varactors 924 a and 924 b and the inductance of inductor 922 determine the resonant frequency of tank circuit 920, which determines the frequency of the oscillator signal from VCO 140. Capacitors 926 a and 926 b provide DC blocking to allow nodes Sa and Sb to be biased at the desired voltage. Resistors 928 a and 928 b provide isolation for nodes Sa and Sb.

Loop filter 712 receives the currents from current sources 722 and 732 in charge pump 120 and generates the control voltage V_(CTRL) as well as the noise cancellation voltage V_(N) for varactors 924 a and 924 b within VCO 140. Node A is low impedance and carries the control signal from loop filter 712. Node B is high impedance and has low leakage and essentially no signal swing. The non-inverting input of op-amp 736 may be coupled to a reference voltage V. The DC voltage at nodes Sa and Sb would then be equal to V. The bias voltage for varactors 924 a and 924 b may thus be set by applying an appropriate reference voltage to the non-inverting input of op-amp 736.

FIG. 9 shows an exemplary VCO that may be controlled by a dual-path loop filter with noise cancellation. The dual-path loop filter described herein may also be used with other VCOs as well as other types of oscillators such as, e.g., current controlled oscillators (ICOs), voltage controlled crystal oscillators (VCXOs), and so on. The dual-path loop filter described herein may also be used for various types of PLLs such as integer-N PLL (where frequency divider ratio N in FIG. 1 is an integer value) as well as fractional-N PLL (where N is not an integer value). The first and second signal paths may be designed to provide the desired transfer functions. For example, capacitor C₂ in the first signal path may be replaced with a higher order lowpass filter to achieve sharper roll-off for a fractional-N PLL.

FIG. 10 shows an embodiment of a process 1000 for performing loop filtering with noise cancellation. First and second signals are generated with first and second current sources, respectively, in a charge pump (block 1012). The second current source provides alpha times less current than the first current source, where alpha is greater than one and may be, e.g., 10 or more. The second signal is a scaled version of the first signal and is smaller than the first signal by a factor of alpha.

The first signal is passed through a first signal path that provides a first transfer function (e.g., a lowpass response) for the first signal (block 1014). The second signal is passed through a second signal path that provides a second transfer function (e.g., an integration response) for the second signal (block 1016). The first signal path may comprise a resistor and a first capacitor. The second signal path may comprise a second capacitor that is scaled smaller by a factor of alpha due to the second signal being scaled smaller by alpha. An op-amp is coupled to the first and second signal paths and is configured to facilitate summing of signals from the first and second signal paths to generate a control signal having op-amp noise (block 1018). The op-amp and the first and second signal paths are part of a loop filter and may be coupled in various manners, e.g., as shown in FIGS. 7A through 7D.

A noise cancellation signal is generated with a noise cancellation path that is coupled directly or indirectly to the op-amp (block 1020). The noise cancellation path may comprise a wire line coupled to the op-amp or the second signal path or may comprise additional circuit elements. The noise cancellation signal is used to cancel the op-amp noise in the control signal. The control signal and the noise cancellation signal are applied to an adjustable circuit element, e.g., a varactor (block 1022).

For clarity, a loop filter with two signal paths and employing noise cancellation has been described above. Noise cancellation may also be used for loop filters with more than two signal paths. For example, a multi-path loop filter may comprise one or more signal paths that filter a control signal used for tracking frequency error in a VCO, another one or more signal paths that filter a sweep signal used for acquisition, yet another one or more signal paths that filter an adjustment signal used to center the frequency of the VCO, and so on.

The loop filter with noise cancellation described herein may be used for various electronics circuits. The use of the loop filter with noise cancellation for a wireless communication device is described below.

FIG. 11 shows a block diagram of an embodiment of a wireless device 1100 in a wireless communication system. Wireless device 1100 may be a cellular phone, a terminal, a personal digital assistant (PDA), a handset, or some other device. The wireless communication system may be a Code Division Multiple Access (CDMA) system, a Time Division Multiple Access (TDMA) system, a Frequency Division Multiple Access (FDMA) system, a Global System for Mobile Communications (GSM) system, an Orthogonal FDMA (OFDMA) system, and so on.

Wireless device 1100 includes a digital processor 1110 and a transceiver 1130 that supports bi-directional communication. Digital processor 1110 may be implemented with one or more application specific integrated circuits (ASICs), and transceiver 1130 may be implemented with one or more RF integrated circuits (RFICs).

Within digital processor 1110, an encoder 1112 processes (e.g., formats, encodes, and interleaves) data to be transmitted, and a modulator (Mod) 1114 further processes (e.g., modulates and scrambles) the coded data to generate data chips. Within transceiver 1130, a transmit (TX) baseband unit 1132 performs baseband processing such as digital-to-analog conversion, filtering, amplification, and so on. A mixer 1134 upconverts the baseband signal to RF. A TX RF unit 1136 performs signal conditioning such as filtering and power amplification and generates an RF modulated signal, which is transmitted via an antenna 1140. For data reception, a receive (RX) RF unit 1142 receives an input RF signal from antenna 1140 and performs signal conditioning such as low noise amplification and filtering. A mixer 1144 downconverts the conditioned RF signal from RF to baseband. An RX baseband unit 1146 performs baseband processing such as filtering, amplification, analog-to-digital conversion, and so on. A demodulator (Demod) 1116 processes (e.g., descrambles and demodulates) the input samples from unit 1146 and provides symbol estimates. A decoder 1118 processes (e.g., deinterleaves and decodes) the symbol estimates and provides decoded data. In general, the processing by data processor 1110 and transceiver 1130 is dependent on the design of the wireless system.

A processor 1120 may support various applications such as video, audio, graphics, and so on. A controller/processor 1160 directs the operation of various processing units within wireless device 1100. A memory 1162 stores program codes and data for wireless device 1100.

A VCO/PLL 1122 generates clock signals for the processing units within digital processor 1110. A VCO/PLL 1150 generates a transmit LO signal used by mixer 1134 for frequency upconversion and a receive LO signal used by mixer 1144 for frequency downconversion. VCO/PLL 1122 and VCO/PLL 1150 may each employ a loop filter with noise cancellation to improve noise performance. A reference oscillator 1164 generates a reference signal for VCO/PLL 1122 and/or VCO/PLL 1150.

The loop filter with noise cancellation described herein may be implemented in an analog IC, an RFIC, an ASIC, a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a processor, a controller, a micro-controller, a microprocessor, and other electronic units. The loop filter with noise cancellation may be implemented in various IC process technologies such as N-MOS, P-MOS, CMOS, BJT, GaAs, and so on. The loop filter may also be implemented with discrete components.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein. 

What is claimed is:
 1. An apparatus comprising: a loop filter comprising an operational amplifier (op-amp) and configured to generate a control signal having op-amp noise and to generate a noise cancellation signal used to cancel the op-amp noise in the control signal; and a voltage-controlled oscillator (VCO) coupled to the loop filter and comprising at least one adjustable circuit element to vary an oscillating frequency of the VCO, the at least one adjustable circuit element being applied with the control signal and the noise cancellation signal from the loop filter.
 2. The apparatus of claim 1, wherein the loop filter is configured to receive first and second signals, to provide a first transfer function for the first signal, and to provide a second transfer function for the second signal.
 3. The apparatus of claim 2, wherein the first transfer function is a lowpass response, and wherein the second transfer function is an integration response.
 4. The apparatus of claim 2, wherein the second signal is a scaled version of the first signal and is smaller than the first signal by a factor of alpha, where alpha is greater than one, and wherein the loop filter comprises a capacitor used to obtain the second transfer function and scaled smaller by a factor of alpha.
 5. The apparatus of claim 1, further comprising: a charge pump comprising a first current source to provide the first signal and a second current source to provide the second signal, the second current source providing alpha times less current than the first current source, where alpha is greater than one.
 6. The apparatus of claim 1, wherein the at least one adjustable circuit element comprises at least one varactor.
 7. The apparatus of claim 1, further comprising: a divider configured to divide an oscillator signal from the VCO by an integer divider ratio and provide a feedback signal; and a phase-frequency detector configured to determine phase error between the feedback signal and a reference signal.
 8. The apparatus of claim 1, further comprising: a divider configured to divide an oscillator signal from the VCO by a non-integer divider ratio and provide a feedback signal; and a phase-frequency detector configured to determine phase error between the feedback signal and a reference signal.
 9. An integrated circuit comprising: a loop filter comprising an operational amplifier (op-amp) and configured to generate a control signal having op-amp noise and to generate a noise cancellation signal used to cancel the op-amp noise in the control signal; and a voltage-controlled oscillator (VCO) coupled to the loop filter and comprising at least one adjustable circuit element to vary an oscillating frequency of the VCO, the at least one adjustable circuit element being applied with the control signal and the noise cancellation signal from the loop filter.
 10. The integrated circuit of claim 9, wherein the loop filter is configured to receive first and second signals, to provide a first transfer function for the first signal, and to provide a second transfer function for the second signal.
 11. The integrated circuit of claim 10, wherein the second signal is a scaled version of the first signal and is smaller than the first signal by a factor of alpha, where alpha is greater than one, and wherein the loop filter comprises a capacitor used to obtain the second transfer function and scaled smaller by a factor of alpha.
 12. A wireless device comprising: a loop filter comprising an operational amplifier (op-amp) and configured to generate a control signal having op-amp noise and to generate a noise cancellation signal used to cancel the op-amp noise in the control signal; and a voltage-controlled oscillator (VCO) coupled to the loop filter and comprising at least one adjustable circuit element to vary an oscillating frequency of the VCO, the at least one adjustable circuit element being applied with the control signal and the noise cancellation signal from the loop filter.
 13. The wireless device of claim 12, wherein the VCO generates an oscillator signal used to derive clock signals for digital circuitry.
 14. The wireless device of claim 12, wherein the VCO generates an oscillator signal used for frequency upconversion or downconversion. 